Vhdl code Model a full-subtractor in VHDL at the structural gate level. The specifications for the f

Vhdl code
Model a full-subtractor in VHDL at the structural gate level. The specifications for the ful subtractor model are given below: You are allowed to use only the following logic gates in your full-subtractor design: NOT, 2-input AND, 3-input OR and 3-input XOR The propagation delay for each NOT gate is 1 ns The propagation delay for each OR gate is 2 ns .The propagation delay for each AND gate is 2 ns The propagation delay for each XOR gate is 3ns Compile and load your VHDL full-subtractor program using ModelSim/Questa Sim .Using ModelSim, simulate the full-subtractor design for the following cases: 000, 001, 010, 011, 100, 101, 110, 111, XHL, HHL, L-L, ZOX Use the ModelSim/Questa Sim force command in order to assign values to the input signals of your design

 

Looking for a Similar Assignment? Let us take care of your classwork while you enjoy your free time! All papers are written from scratch and are 100% Original. Try us today! Use Code FREE15