(a) What is the maximum number of words of data from the main memory that can be stored in the cache at any one time?
(b) How many bits of the address are used to select which line of the cache is accessed?
(c) How many bits wide is the tag field?
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(d) Briefly explain the purpose of the one-bit V field associated with each cache line
(e) Assume that location 0xCF120 was present in the cache. Using the row and column labels from the figure, in what location(s) could we find the data from that location? What would the value of the tag field have to be for the cache row in which the data appears?
(f) Can data from location 0xF6768 and 0xF67F8 be present in the cache at the same time? What about the data from locations 0xB20738 and 0x2034? Explain?
(g) When an access causes a cache miss, how many words need to be fetched from memory to fill the appropriate cache location? 4. The diagram below illustrates a blocked, direct-mapped cache for 32-bit data words with 32-bit byte addresses 32-bit address from CPU DATA DATA DATA DATA V TAG .00 .01 -10 Row 15 Row 14 Row 13 Row 12 Row 11 Row 10 Row 9 Row 8 Row 7 Row 6 Row S Row 4 Row 3 Row 2 Row 1 Row 0 32 32 32 32 DATA HIT